An arXiv version 1 preprint dated 25 Aug 2026 describes a benchmark suite of 20 designs for physical-design research on heterogeneous 2.5D and 3D systems. The suite is intended to provide a common set of cases for examining how complex chip packages are arranged and connected.
The project responds to a gap identified in the paper: limited availability of publicly accessible, scalable 3D physical-design benchmarks for reproducible evaluation. In this setting, physical design concerns arranging and connecting chiplets, dies and substrates in a system-in-package.
From reusable parts to complete packages
Construction follows two phases. First, the authors define a reusable library of virtual chiplet models. They then compose those elements into a graded suite of system-in-package designs. The common parts give the cases a shared basis while the assembled arrangements can vary.
The library covers compute, memory, I/O, analog and substrate components. It defines five virtual active-die templates and two substrate templates. Together, these elements provide the component types used to assemble the benchmark designs.
An infrastructure layer links the cases to a conversion framework that translates CATCH designs into an industry-standard benchmark representation. The designs are expressed in the CATCH XML schema, which supports arbitrary stack hierarchies, face- and back-side connectivity, through-silicon-via (TSV) pass-through signaling, buried dies and routing constraints at the substrate level.
A spread of designs, with built-in stress cases
The 20 designs are organized into four categories: foundational 2.5D configurations, basic 3D stacking topologies, complex hybrid architectures and model-stress variants. The structure runs from core packaging arrangements to cases that deliberately change the conditions a design flow must handle.
The stress-test variants perturb design parameters related to congestion, NRE amortization, assembly-process selection, placement regularity and chiplet-count scaling. NRE amortization means spreading one-time engineering costs across designs. The preprint describes these variants as exercises for a flow under changed conditions, but reports no performance results for them.
A release with questions still open
The release includes 3Dblox testcase descriptions and supporting open-source physical-design collateral described as necessary to reproduce and extend the benchmarks. The paper states that the complete benchmark design set is publicly available through the Dryad repository under DOI 10.5061/dryad.76hdr7tb6. It also says the authors hope the release will enable reproducible comparison across academic and commercial 3D design methodologies. That is an intended use, not a demonstrated outcome in the preprint.
The evidence in the paper stops at benchmark construction, testcase composition, file formats and repository availability. It does not report how existing physical-design algorithms perform across the 20 cases, and it does not quantify how representative the CATCH-derived configurations are beyond the suite.
For now, the contribution is a shared starting point for evaluating tools and design flows, coupled with an explicit aim of making comparisons more reproducible. Whether the suite achieves that role in practice remains open. Later work will need to test methods across the 20 designs, examine their coverage against broader chiplet and packaging choices, and extend the suite to additional objectives.
Paper data and sources
Original title: An Open-Source Benchmark Suite of 3D-IC Testcases
Authors: Rohan Soni, Jooyeon Jeong, Alexander Graening et al.
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-08-25
DOI: Not available
Original paper · Full text