A new compiler for quantum error correction on neutral-atom arrays produced much shorter modeled execution schedules than two existing methods in the study’s benchmarks. The reported gains came from computational execution plans and circuit-level noise simulations, not from a run on a physical neutral-atom processor.
The work is an arXiv preprint dated 20 August 2026. It examines quantum low-density parity-check codes, or qLDPC codes, including hypergraph-product (HGP) code instances and one-dimensional syndrome-extraction schedules generated from randomly created regular Tanner graphs.
A compiler built around the code’s shape
ONEX exploits HGP product structure by splitting syndrome-extraction interactions into independent row and column one-dimensional subproblems, then composing those subproblems on the array’s Cartesian geometry.
Its pipeline combines a satisfiability-modulo-theories solver to search for short schedules, mixed-integer linear programming to compact movement, iterative feedback and parallel solver runs. The result is a compiler that treats schedule depth and movement as linked optimization problems.
The main tests used existing HGP code instances and one-dimensional schedules made by edge-colouring randomly generated classical Tanner graphs with degree patterns of 3 and 4. The comparisons were made against the constructive method reported by Xu and colleagues and against Enola, a general two-dimensional compiler, under the same neutral-atom array architecture.
Large gains in the reported benchmarks
For the HGP application benchmarks, ONEX cut execution depth by factors of 28.1 to 38.0 compared with Enola and by 6.8 to 8.0 compared with the Xu method. The corresponding modeled clock-rate gains were 29.8 to 42.1 times over Enola and 3.7 to 6.1 times over Xu’s approach.
The one-dimensional tests showed a similar pattern. ONEX used four to five rearrangement steps—an 86.8% to 88.9% reduction against Xu’s method—and its execution duration was 8.0 to 8.9 times shorter than Xu’s and 4.4 to 8.7 times shorter than Enola’s across the tested sizes.
An analysis of the pipeline suggested that most of the movement savings arrived early. The initial depth-optimization phase reduced movement distance by 68% to 71%; compaction added 11% to 16%, and local refinement added a further 17% to 40%. Global refinement produced only marginal gains in the reported tests.
The authors also separated the effect of solver-based local optimization from the effect of ONEX’s broader formulation. Adding solver-based optimization to the baseline improved depth by 3.43 to 3.94 times and duration by 1.93 to 2.15 times. ONEX then improved depth by a further 1.78 to 2.33 times and duration by 1.77 to 2.88 times relative to that enhanced baseline.
The compilation bill comes later
The main trade-off was time spent preparing the schedule. Near the reported practical boundary, a depth-six solution for an HGP instance with 2,500 data qubits took a mean of 12.8 hours to compile. A larger instance with 4,225 data qubits averaged 17.6 hours for a depth-eight solution, and the paper reports that compilation time grew exponentially with problem size.
The scaling analysis used parallel solver runs, but the reported times still depended on solver settings and parallelism. The results therefore do not establish that compilation remains practical at arbitrarily larger problem sizes.
A different layout changes the trade-off
The paper also evaluated ONEX in zoned-layout benchmarks. In single-round comparisons at the 2,500-qubit size, it reduced duration by more than 1,000 times against the general PowerMove and ZAC flows. Against decomposed versions of those tools, the reported gains were 37.1 to 71.5 times over PM-D and 9.3 to 12.8 times over ZAC-D.
But the zoned design was not faster on every measure. It cut movement distance by more than half relative to ONEX, while total duration was 3.4 to 5.7 times higher. The paper attributes that overhead to the extra loading and unloading required by the layout.
For one representative LP-code case, ONEX-Z was estimated to reduce intra-lift rearrangement time by about 46%, inter-lift time by about 28% and total cycle duration by about 10%. That result is a single case study rather than a broad evaluation of LP codes.
Modeled fidelity also improved
The study’s noise simulations pointed to a second possible benefit: lower modeled logical error rates, meaning fewer simulated errors remaining in the encoded information. Under the specified circuit-level noise model and decoder, the estimated threshold rose from 1.26 × 10−2 to 1.51 × 10−2, a 19.5% increase. At a physical error rate of 0.005, logical error rates were 1.23 to 1.85 times lower, with median reductions of 43.7% for the largest HGP codes and 17.9% for the smallest.
Those figures describe a model, not a measured property of neutral-atom hardware. They depend on the chosen noise assumptions and BP-OSD decoder, and the study reports no uncertainty intervals for the performance or fidelity estimates.
What remains untested
The paper does not report runs on a physical neutral-atom processor. Its clock rates, execution durations and fidelity results are modeled or simulated, and the zoned-layout analysis did not evaluate fidelity. The zoned comparisons were also limited to single-round circuits because PowerMove and ZAC do not natively support multi-round rearrangement.
The evaluation focused on quantum-error-correction memory and syndrome extraction. Fault-tolerant logic operations were discussed but not compiled or evaluated, and the LP-code result covered one representative case. The paper leaves open how the gains would change across other code families, neutral-atom architectures, noise models and decoders.
Across the reported comparisons, the paper provides ratios, percentage changes, ranges, means and medians rather than inferential statistical tests or confidence intervals. The figures are descriptive of the selected benchmarks and specified model, not formal uncertainty estimates.
The next test is on physical neutral-atom processors, where transport, gate, loss and decoherence behavior can be measured directly. The study also leaves open how zoned shuttling affects logical fidelity, how the method performs on fault-tolerant logic operations and broader code families, and how compilation can be managed beyond the reported size boundary.
Paper data and sources
Original title: Architecture and Compilation Co-Design for High-Rate Quantum Product Codes on Neutral Atom Arrays
Authors: Adrian Liu, Wan-Hsuan Lin, Daniel Bochen Tan et al.
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-08-20
DOI: Not available
Original paper · Full text