A preprint describes a way to simplify parity-check circuits—the circuits used for syndrome extraction—for three qLDPC code families: Lifted Product, Balanced Product and Quantum Tanner codes. The method uses symmetries inherited from how the codes are built, solves a smaller scheduling problem, and transfers that schedule to the full code.
For every Quantum Tanner case tested, the resulting circuits reached the paper’s lower bound for CNOT depth—the number of sequential layers of controlled-not operations. The authors describe those cases as depth-optimal, but that finding is limited to the instances examined.
The problem is a graph schedule
The approach treats a parity-check circuit as a graph-scheduling task. Edges that meet at the same vertex must receive different time labels so the circuit remains valid, while an additional condition called properness governs how ancilla information propagates and avoids contamination.
The framework first removes construction-induced edge symmetries, builds the schedule on a reduced graph, and then lifts the solution to the full code. For Quantum Tanner codes, the reduced edge-coloring problem depends on the underlying classical codes rather than on the group or multisets used in the construction.
Depth at the bound
The paper states that the best CNOT depth lies between a lower bound, Δ, and an upper bound, ΔX + ΔZ. For Lifted Product codes, the reported total is ΔA + 2⌈ΔB/2⌉: it equals Δ when at least one of ΔA and ΔB is even, and is Δ + 1 when both are odd.
In the both-odd case, extensive numerical tests suggest that the lower bound cannot be reached and that the extra layer is the true minimum. That conclusion is not presented in the supplied analysis as a proof.
The analytical construction is reported as provably optimal or near-optimal for Lifted Product and Balanced Product codes. The Quantum Tanner evaluation covered reported codes up to nearly 600 data qubits, with every tested case returning a schedule at the lower bound.
A scheduling result, not a hardware test
The evidence comes from analytical graph constructions and CP-SAT optimization of reduced Quantum Tanner problems. It is therefore a result about circuit scheduling; no quantum-hardware operation, circuit-level noise analysis, logical-error result, decoder-performance result, or threshold measurement is reported.
The circuit formulation imposes no restriction on which qubits can connect, so the reported schedules do not establish hardware feasibility. The supplied analysis also does not give the number of Quantum Tanner instances, their individual depths, or solver runtimes and settings, while detailed Balanced Product derivations are deferred to supplementary material.
The authors interpret the findings as evidence that algebraic structure in good qLDPC codes can substantially simplify parity-check circuits. They leave open whether the both-odd Lifted Product case can be settled analytically and how connectivity, noise, hook errors and decoder objectives would change the best schedule.
Publication note
The document is an arXiv preprint, version 1, identified as arXiv:2608.19917v1 and dated 20 Aug 2026.
Paper data and sources
Original title: Disassembling qLDPC codes for depth-optimal parity-check circuits
Authors: Minh T. P. Nguyen, Maximilian Rimbach-Russ, Stefano Bosco
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-08-20
DOI: Not available
Original paper · Full text