The highest reported speedup was 92.53 times in an arXiv preprint testing an AI-assisted workflow that split application tasks between a general-purpose processor and a field-programmable gate array. It came in the communication-aware case of the CAMC workload, where Gemini selected an all-FPGA partition. The evaluation also included CNNImageProc, four objective directions and three large language models, or LLMs.
The setup covered two representative workloads on an AMD ZCU104 FPGA-GPP platform. Each workload-objective-LLM configuration was run in five independent sessions, and a run counted as successful only when it produced a valid allocation, passed FPGA implementation and passed on-board functional validation. Hardware metrics came from implementation reports, while end-to-end latency was measured on board.
How the allocation is built
Gen-TAS represents an application as an ordered task graph, meaning tasks connected by dependencies. Each candidate partition assigns every task to either the GPP or the FPGA. The workflow builds design context, analyses tasks and dataflow, and uses retrieval-augmented generation, or RAG, to generate and select partitions with help from a knowledge base.
The retrieval step uses token-based cosine similarity to rank knowledge-base records, then takes the 12 highest-scoring entries. By default, it generates three ranked candidates. Before selection, deterministic checks look for valid and unique task assignments, disjoint FPGA and GPP sets, and a contiguous FPGA placement in the original execution order. Validated candidates and their rationales are presented to the designer, and the selected strategy is then implemented and measured.
When the objective changed, the partition changed
For CNNImageProc, constrained-latency and communication-aware objectives consistently favoured the reported FFFFG partition. The measured result included a 2.45 times speedup, with LUT, FF, DSP and BRAM use lower by 18.7, 10.2, 68.0 and 27.6 percent, respectively.
For the same workload under power prioritisation, GPT and Claude selected GGFFG. The report recorded a 15.9 percent reduction in FPGA power and lower LUT, FF, DSP and BRAM use by 51.7, 29.9, 92.0 and 55.2 percent, respectively, alongside increased latency.
For CAMC, GFF was selected for most objectives, with a reported 3.53 times speedup, 17.2 percent lower LUT use, 13.2 percent lower FF use, 27.6 percent lower DSP use and 1.8 percent lower FPGA power. Under the communication-aware objective, Gemini instead selected the all-FPGA FFF partition and recorded the highest reported speedup, 92.53 times.
Under the strict-resource objective, GPT selected FGG for CAMC. The report recorded reductions of 26.6, 20.3, 72.4 and 93.9 percent in LUT, FF, DSP and BRAM use, respectively, along with a 1.38 times speedup and a 5.4 percent reduction in FPGA power. The paper says the strict-resource limits were intentionally outside the characterised feasible power region.
Repeatability had limits
Repeatability was tested across 24 workload-objective-LLM configurations. In 22, the dominant partition was reproduced in at least four of five runs; 15 had complete five-of-five consistency.
Generation times varied by model. Mean generation times ranged from 22.161 to 35.994 seconds for Gemini, 58.913 to 71.699 seconds for GPT and 76.910 to 103.820 seconds for Claude. Gemini generally had the shortest reported times in this comparison.
The reported evaluation covered two representative workloads on one AMD ZCU104 platform, using four objective directions and three LLMs. Its validation rules required FPGA-assigned tasks to remain in one contiguous group in their original execution order. The strict-resource limits were deliberately outside the characterised feasible power region.
Publication and access
The supplied document is an arXiv version 1 preprint dated 28 August 2026. It states that source code and supplementary materials are available in a GitHub repository. The work reports support from the UKRI-EPSRC APRIL AI Hub and the 2026 Google DeepMind Research Ready Scheme, with support identified from Google DeepMind, The Hg Foundation, DSIT and the Royal Academy of Engineering.
Paper data and sources
Original title: Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems
Authors: Mary Kong, Yuqin Zhao, Semih Vazgecen et al.
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-08-28
DOI: Not available
Original paper · Full text