A quantum-circuit design that trades extra qubits for shorter simulated runs showed a sharp depth reduction in a modeled 13-spin TMS system. At R = 3, the wider design had 0.48 times the two-qubit depth of a sequential design on a heavy-hex layout and 0.50 times the depth on an all-to-all layout. Its width-depth volume—a combined measure of circuit width and depth—was 0.59 and 0.62 times the sequential value, respectively.
The trade-off was visible in the gate totals. On heavy-hex, the wider circuit used 0.84 times as many two-qubit gates as the sequential version, while on the all-to-all target it used 1.42 times as many. The results come from an arXiv v1 preprint dated 20 Aug 2026, and the circuits were compiled and simulated rather than executed on a quantum device.
A deliberate trade: width for depth
The method is a fan-out compiler for product-formula simulation of Heisenberg-type spin Hamiltonians. It gives interacting spins degree-dependent registers—extra qubits that let matching quantum interactions run in parallel—so the circuit becomes wider but shallower than a sequential implementation. Each register uses a distance-2 repetition code, allowing the circuit to detect—but not correct—a single-qubit bit flip.
In the routing-free analysis, the depth of an interaction block grew logarithmically with the graph's maximum degree—the largest number of direct connections for any spin—rather than with the number of edges. The qubit cost was quadratic for fully connected systems and linear for sparse topologies such as chains.
The main comparison used 32 Trotter steps—the repeated short steps used in the simulation—for the 13-spin TMS star, a 19-spin HMPA star model, tetraethylsilane, a two-hub phosphine model and other molecular or model systems. Both the sequential and fan-out strategies used the same term sequence and simplification rules before being mapped at optimization level 3 to a heavy-hex model of ibm aachen and an all-to-all trapped-ion model. Heavy-hex results used 1,024 transpilation seeds per cell; all-to-all results were deterministic.
The graph—and the machine—mattered
Across the listed systems, every all-to-all result showed a volume benefit. The reported volume ratio ranged from 0.93 for difluoroheptane, whose maximum graph degree was 6, to 0.46 for tetraethylsilane, whose maximum degree was 20. On heavy-hex, gains appeared when the fan-out register fit into a localized patch of the lattice, so the reported benefit depended on both the interaction graph and the device layout.
The study's central noisy example was a zero-field 13-spin TMS star with 12 protons. It compared a 13-qubit sequential circuit with a 16-qubit fan-out circuit using R = 3, sampled 45 acquisition points and used 4,096 simulated shots at each point.
The benefit appeared at lower noise
The error-detection benefit emerged only along the lower-noise trajectory used in the simulation. At a median two-qubit error of 1.5 × 10−3, no compilation recovered the TMS spectrum. Recognizable comb patterns appeared near 2 × 10−4, and the fan-out circuit after post-selection began to lead in spectral quality from 10−4 while keeping half the two-qubit depth.
At 10−4, the post-selected circuit's correlation with the exact spectrum was 0.70, compared with 0.63 for the sequential circuit. At 5 × 10−5, the corresponding correlations were 0.94 and 0.89, while amplitude retention was 0.54 for the fan-out circuit and 0.39 for the sequential one.
Post-selection came with a sampling cost because some shots were discarded. The acceptance rate was 0.43 at 10−4, corresponding to a 2.3-fold sampling overhead, and 0.63 at 5 × 10−5, with a 1.6-fold overhead. At the lower error rate, paired comparisons reported gains of 0.05 in correlation and 0.14 in amplitude retention, with 95% bootstrap intervals excluding zero.
Still a computer study
The calculations were checked against an independent SPINACH simulation: the exact signal decays agreed to 5.2 × 10−6 per point, and the zero-error noisy pipeline matched the noiseless reference within shot noise. That supports the internal simulation and reference-processing chain, but it does not test execution on physical hardware.
The reported noise result is tied to the scaled calibration trajectory used in the model. The distance-2 redundancy detects selected bit flips, while phase flips, leakage and readout errors are outside the stated protection. The work therefore remains a computational resource comparison and noise simulation, not a hardware demonstration.
Paper data and sources
Original title: Logarithmic depth compression of Heisenberg Hamiltonian simulation by fan-out parallelization, with built-in error detection
Authors: Artemiy Burov, Clément Javerzac
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-08-20
DOI: Not available
Original paper · Full text