Jitter—the variation in measured timing—was consistently 1 microsecond on an RP2040 microcontroller in a preprint's tests, but reached approximately 905 microseconds on AMD Linux. Across three simulated microcircuits, the paper reports expected dynamical signatures, formal timing bounds and worst-case response times matching analytical predictions.
The evaluation was computational: it covered three modeled microcircuits, implemented in C++ and cross-validated on workstation and microcontroller platforms. The document is labeled arXiv version 1, dated 20 Aug 2026.
A discrete model with a continuous check
At its center is a five-place, five-transition Petri net. The formal structure lets the model's states, firing events and timing relationships be checked mathematically; structural analysis reported it as live, with no deadlocks.
Parameters from the Petri neuron were mapped to continuous leaky integrate-and-fire equations, allowing the two descriptions to be compared by firing rate. For the reported parameterization, symmetric relative errors stayed below 20 percent in spontaneous and active firing and approached zero above 100 Hz.
The platform mattered
Timing was measured as signed error in 10,000 trials at five nominal delays for each platform. The RP2040 result was consistently 1 microsecond of jitter; AMD Linux was delay-dependent and reached approximately 905 microseconds.
The contrast limits how broadly the timing result can be read. The evidence supports formal bounds for the reported model and tested setups; it does not establish the same behavior across arbitrary hardware, operating systems, workloads or network sizes. The delay-dependent Linux result shows that platform conditions are part of the picture.
Three simulations, three signatures
In the feedback-inhibition case, the simulation was described as producing rhythmic PING activity in the 30–80 Hz gamma range. Excitatory neurons fired at 9-millisecond intervals in 86 percent of reported events and at 15 milliseconds in 14 percent; inhibitory neurons fired every 75 milliseconds, and the reported loop latency was 22 milliseconds. The authors say the steady-state timing condition held at a 27-millisecond bound, guaranteeing bounded-cycle arrival of inhibitory feedback in the simulated loop.
The lateral-inhibition simulation reported a 9-millisecond competition-resolution bound independent of input contrast.
The hierarchical feature detector showed a 2:1 preferred-orientation spike-count ratio and a selectivity index of 0.33. In a horizontal-line test, the first horizontal complex-cell response came at time 6, the vertical response at time 9, producing a gap of 3 timesteps.
Still a prototype
These cases are demonstrations inside a formal simulation framework. They do not amount to evidence that the model reproduces biological neural activity; the reported evaluation is limited to the three modeled circuits and platform timing trials.
The authors identify several constraints: the model omits the relative refractory period, integer token quantization can introduce error, synaptic weights are static, and scalability to large networks was not characterized.
That leaves practical questions about comparison with biological recordings or established circuit benchmarks, representation of synaptic plasticity and adaptive quantization, and the scheduler's behavior on large or distributed networks. The current report supports the simulations and measurements described, not a general claim about large-scale deployment.
Paper data and sources
Original title: Petri Net Description of Biological Neural Circuits for Fast Hardware Prototyping
Authors: Carlo daCunha, Rodrigo Pena, Marcos Turqueti
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-08-20
DOI: Not available
Original paper · Full text