A chip-scale photonic circuit has demonstrated a basic form of memory for optical computing, retaining a logic state and changing it when instructed by a clock. The preprint describes a photonic sequential logic circuit family built from photodetector microring resonators, or PD-MRMs, with photonic D flip-flops, set-reset latches and D latches. In the D-latch test, the device held its stored state when the clock input CP was at logic zero and tracked the data input D when CP was at logic one.
The flip-flop design used two cascaded D latches with optical clocks at the same frequency but opposite phase. It captured the data input only at the rising edge of the clock, operating as a positive-edge-triggered device.
The chip was tested as a logic system
At the device level, the photodetector reached a responsivity of 0.8 A/W under a 3 V forward bias, and the output extinction ratio, a measure of separation between its optical signal levels, was 0.4 dB higher than the input. In a separate set-reset test at 50 MHz, using aperiodic R and S inputs, the generated output sequences agreed with the designed Boolean truth table.
The demonstrations moved beyond individual logic elements. A synchronous sequence detector used a 4-bit shift register made from four cascaded photonic D flip-flops under a single global clock, and measured waveforms showed real-time identification of target data patterns. A 4-bit asynchronous counter operated without a global clock, toggled once for every two input-clock transitions, divided frequency by two and achieved modulo-16 counting after four cascaded stages.
A simulated drone test put the memory to work
For an application test, the photonic sequential circuits were used in a trained optical logic neural network deployed in a simulated flight controller for end-to-end testing in a complex three-dimensional environment. The network took in three consecutive frames, each 16 by 16 pixels, represented as spatio-temporal binary images.
On dynamic obstacle-avoidance samples, the optical logic neural network achieved 98.64% overall classification accuracy. In the highly dense scenario, the sequential system recorded a 97.7% navigation success rate, compared with 40.9% for the purely feedforward baseline. The paper reports that gap as a 56.8% absolute increase.
Those navigation figures come from the simulated flight-controller test, not from a physical drone flight. They show how the sequential system performed in the reported dense scenario, but they do not establish how it would perform in other environments.
The second test generated text
A second demonstration used the circuits for language generation. The position of each photonic D flip-flop stage supplied positional context, and the resulting states were fed into a feedforward nanoGPT autoregressive loop, which uses earlier sequence states as context for later outputs. The hardware preserved its signal extinction ratio after 256 stages of physical cascading and shifting.
Training curves reached stable convergence at 1,500 epochs. Beyond an 8-character context, spelling accuracy stabilized above 85%; under the study's stated exclusions, core spelling accuracy exceeded 90%, while style fidelity was 70%.
The supplied results cover the reported context setting and scoring rules, while the drone test remains simulated. Together, they provide application-level demonstrations of stateful photonic processing, but broader generalization is not established by these tests.
Paper data and sources
Original title: Photonic sequential logic circuits for stateful intelligence
Authors: Jingcheng Li, Wenkai Zhang, Jialong Zhang et al.
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-09-29
DOI: Not available
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