An experimental compiler generated FPGA hardware for a 302-neuron C. elegans network that closely followed a full-precision reference, according to a preprint. In the paper’s reported comparison, the FPGA ran the test 392 times faster than NEST, 3,641 times faster than Brian2 and 143,971 times faster than jNeuroML.
The system, called Syn2Logic, is presented as a prototype for an end-to-end flow that takes computational-neuroscience descriptions toward automated FPGA and ASIC generation. It transforms source into RTL, the low-level form used to describe digital circuitry, with a Flex-generated scanner and a hand-written recursive-descent parser.
The first test was numerical fidelity
Before the performance comparisons, the study checked whether the generated models behaved like their software references. The neuron evaluation covered four models and compared them with Brian2 using normalized root mean square error, or NRMSE, a measure of the gap between numerical traces. The high-fidelity leaky integrate-and-fire variant matched the sampled 380-pA rheobase, the current at which the model starts firing, and reported as little as 0.4% NRMSE.
Synaptic plasticity was tested separately with Pairwise STDP, Triplet STDP, RSTDP and BCPNN under a specified induction protocol. PairSTDP’s Q2:8 format produced 3.5% NRMSE for the fused case and 4.1% for the non-fused case. TripletSTDP’s Q2:9 format produced 2.8% fused and 3.5% non-fused, while RSTDP’s Q2:9 format produced 1.30% fused and 0.20% non-fused. For BCPNN, the reported values were 0.92% for the non-fused case and 3.5% for the fused case.
A network test
In the network-level validation, bit-exact RTL output had a 0.9967 spike-train correlation with the full-precision reference and a 0.94% windowed error. The paper also estimated a further 2.26-fold speed-up for a hypothetical ASIC over the FPGA if the chip were taped out.
The software comparison depended on the stated simulator and server configurations. The reported ratios therefore describe the conditions used for this test.
Sudoku exposes the trade-off
The Sudoku experiment used randomized Latin-hypercube-style sampling over model parameters and re-optimized the hardware operating point at the target fixed-point precision, rather than merely quantizing the floating-point solution.
On 46 Vaasa puzzles, the solver correctly solved every puzzle. Its total FPGA time was 6.19 milliseconds, compared with 142.5 milliseconds for CP-SAT and 173.2 milliseconds for SCIP. A hypothetical ASIC total was 1.80 milliseconds. tdoku completed the set in 82.3 microseconds, so it remained faster under the reported timing comparison. Startup and puzzle-configuration time were excluded.
The reported tests also solved all 42 Euler-96 puzzles and all 1,465 puzzles in TOP1465. For TOP1465, the FPGA total was 3.94 seconds and the hypothetical ASIC total was 1.14 seconds, while tdoku took 12.275 plus or minus 0.008 milliseconds. These results do not establish that the generated hardware was faster than tdoku across all puzzles.
MNIST tells a more mixed story
MNIST provided a separate image-classification workload. The study used 60,000 training images and 10,000 test images with a 110,000-parameter multilayer perceptron. Its initial test accuracy was 97.61%. After 80% pruning, accuracy was 97.23%; after 90% pruning, it was 95.06%.
Hardware results varied by design point. The measured MAX10 system reached 93.80% accuracy, a maximum clock of 45.28 MHz and image latency of 581 nanoseconds. A preliminary Agilex7 design reached 97.07%, 214.82 MHz and 116 nanoseconds, while the ASAP7 estimate was listed at 97.07%, 491 MHz and 51 nanoseconds.
The reported energy figures were up to 1.11 GFPS per watt for the ASAP7 estimate and 5.60 MFP-S per watt for the measured MAX10 system. The paper states that MAX10 was 1.5 times more power-efficient than IBM TrueNorth, but the comparison uses different architectures and measurement boundaries. Because the MAX10 power measurement covered the full system-on-chip, it is an upper bound for the classifier alone.
What the study does not settle
The evidence is limited to the evaluated neuron and synapse models, the 302-neuron C. elegans network, the Sudoku benchmark sets and the MNIST hardware tests. The ASIC figures are estimates rather than measurements from manufactured silicon. The protocols and simulations were deterministic and reproducible from the supplied generators, compiler flags and simulation scripts, with state traces and NRMSE maps archived as machine-readable CSV.
The manuscript is a preprint. The work was supported by the Swedish Research Council’s Project Building Digital Brains under Grant 2021-04579.
Paper data and sources
Original title: Syn2Logic: End-to-End Neuromorphic Design Automation
Authors: Artur Podobas
Journal/Repository: arXiv
Status: Preprint, not yet peer-reviewed
First online: 2026-08-26
DOI: Not available
Original paper · Full text