The study reports that the devices' conductance — the electrical reading used to track their state — showed no tendency to drift after 100,000 non-coincident half-voltage pulses, the partial-voltage signals used to test unwanted updates. At the longer exposure of 1 million pulses, however, high-conductance states showed a downward disturbance. The central question was whether such arrays could support fully parallel in-memory neural-network training while suppressing unwanted changes in cross-point weights.
A device built for fast analog updates
The platform used one-transistor/one-resistor (1T1R) cells integrated with 350-nanometre silicon technology and a CMO/HfOx bilayer. Its reported bidirectional analog switching used 60-nanosecond pulsed cycling at +1.6 volts and -2.3 volts for the two update directions.
For the single-cell disturbance experiment, the researchers applied four trains of 100 pulses: non-coincident up, coincident up, non-coincident down and coincident down. The pulses were +1.4 volts or -1.9 volts and lasted 2.5 microseconds. The same work reported retention of 32 intermediate conductance states for 100 seconds and endurance exceeding 100 million cycles.
What the simulations showed
To examine the device response, a three-dimensional COMSOL finite-element model solved continuity and Joule-heating equations in steady state. It showed temperature concentrated around the conductive filament in the CMO layer, alongside a highly nonlinear conductance response and no conductance change when half-voltage pulses were applied.
The number that mattered
The study summarized unwanted update behaviour with a non-linearity factor called k; smaller values represented less disturbance in the analysis. After 100,000 disturbance pulses, k values from 15 devices varied by up to 0.05. The mean was below 0.005 in both directions, and the standard deviation was below 0.025.
The learning result was simulated
The neural-network test was software-based. It used conventional stochastic gradient descent, or SGD, with a three-layer network of 784, 256 and 10 neurons containing 203,264 analog memories. The setup used 10,000 training images and 10,000 unseen test images.
With the ideal no-disturbance setting k=0, simulated test accuracy was 90.6%. It was 89.08% with the device-model value k=0.005, and 48.82% with k=0.2, the disturbance-prone model.
Contour analysis reported that k below 0.01 was required for successful convergence, and that asymmetry between the upward and downward factors worsened learning performance. A measured device-to-device noise level of 0.18 was reported to impose a negligible training-accuracy penalty. A simulation using a TT algorithm reached 95.2% learning accuracy.
An array demonstration, not hardware training
The hardware demonstration itself used a 5 x 4 array for parallel letter mapping. It sent stochastic pulses with probability 0.5 and a bitstream length of 10; the final conductance-change pattern was interpreted as confirming tolerance to update disturbances during parallel crossbar updates.
That result was an array demonstration rather than measured neural-network training on the device. The reported MNIST accuracies came from the software model. The authors interpret the low k values and stable half-voltage response as support for fully parallel in-memory weight updates, but the supplied results do not show a neural network trained on the physical ReRAM array.
Paper data and sources
Original title: Update Disturbance-Resilient Analog ReRAM Crossbar Arrays for In-Memory Deep Learning Accelerators
Authors: Wooseok Choi, Tommaso Stecconi, Donato Francesco Falcone et al.
Journal/Repository: Adv. Sci. 13, no. 4 (2026): e04578
Status: Peer-reviewed
First online: 2026-08-26
DOI: 10.1002/advs.202504578
Original paper · Full text